BIST for Deep Submicron ASIC Memories with High Performance Application
نویسندگان
چکیده
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed.
منابع مشابه
Concurrent BIST for Embedded SRAMs in SoCs
With the progress of deep submicron technology and increasing design complexity, hundreds of memory cores with different size and configuration are embedded in system-on-chips (SoCs). These memory cores occupy a noticeable silicon area and need an efficient and low-cost test methodology. Built-in Self-test (BIST) is a practical solution provides a certain degree of reliability and flexibility. ...
متن کاملEmbedded Memory Bist for Systems-on-a-chip Embedded Memory Bist for Systems-on-a-chip
Embedded memories consume an increasing portion of the die area in deep submicron systems-on-a-chip (SOCs). Manufacturing test of embedded memories is an essential step in the SOC production that screens out the defective chips and accelerates the transition from the yield learning phase to the volume production phase of a new manufacturing technology. Built-in self-test (BIST) is establishing ...
متن کاملAnalog Design in Deep Submicron Cmos Processes for Lhc
Present state-of-the-art CMOS technologies integrate MOS transistors with a minimum gate length of 0.18 Pm0.25 Pm and operate with a maximum power supply of 2.5 V. The thin gate oxide used in these technologies has a high tolerance to total dose effects. Therefore, circuits designed in these technologies using dedicated layout techniques (enclosed layout transistors and guard-rings) show a tota...
متن کاملCapacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Capacitor-couple technique used to lower snapbacktrigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-coup...
متن کاملLI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects∗ KRISHNA SEKAR AND SUJIT DEY
For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2003